Memory Layout Design Lead Engineer

Technical Skills

  • 6+ years of experience of designing and verification of Memory layouts
  • Hands-on experience with layouts of leaf cells like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc for custom macros & compilers.
  • Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies .
  • Hands-on experience with top-level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
  • Able to fix EM/IR-related issues in memory layouts.
  • Good understanding of the development of memory compilers.
  • Excellent knowledge of Different memory architectures. Knowledge of Perl/skill/shell scripting is a plus

Additional Skills:

  • It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem-solving skills and show high levels of initiative.
  • Should be able to mentor junior engineers in the team.

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